Not ruled out, not ruled in

The strained silicon technique, which can speed up transistors by as much as 10 per cent, will definitely scale to the 65 nano generation, he said. And it may work for the 45 nano generation too, MARK BOHR, a senior fellow at Intel said. Further, Intel has not ruled out using silicon on insulator (SOI) in the future – it may be incorporated in the 45 nano generation, but no decision has been made yet. By the end of the next year, Intel should have four fabs producing chips on 300 millimeter silicon wafers. After the Leixlip fab converts during the first half of next year, Intel will also crank up 300mm production in Fab 24 in Arizona. And it may continue swapping this technology in*. Intel will have enough silicon capacity to supply the world and possibly another planet in our solar system, if we find life on Neptune. Bohr said that the move from .13µ (micron) technology to 90 nanometer processes was faster than the previous shift. And he also claimed that there was no problem with yields for the smaller process. He said that Intel had produced a very rapid yield improvement in the last months, using the 90 nano tech.